一、the semiconductor industry environment
Semiconductor industry was born in the 1970s, which was mainly driven by two factors: First, the computer industry to provide more cost-effective memory; second is to meet the business development of new products with specific features and rapid production of ASIC. By the 1980s, the system specifications firmly in the hands of system integrators. Memory devices updated every three years in semiconductor technology, and then was logic device manufacturers. In the 1990s, logic IC manufacturers to accelerate the introduction of new technologies to speed the generation of updated every two years, after keeping the memory manufacturers. Technological advances and enhanced product performance unusual strong correlation between such control over a considerable portion of system performance and profits go to the integrated circuit (IC) manufacturers. They take advantage of this new balance of power, the entire semiconductor industry revenue in this period the average annual growth rate of 17%.
The first decade of the 21st century, the semiconductor industry has formed a new environment:
1. Every two years a new generation of semiconductor technology, resulting in an integrated circuit and millions of transistors to high efficiency, low cost production, so that a chip or in the same package, a lower cost can be extremely complex systems integration . In addition, advances in packaging technology allows us to place multiple chips in the same package. Such devices are defined as SoC (system on chip, SOC) and System-in-Package (system in package, SIP).
2.. IC foundry industry and commerce can be re very attractive cost to provide "a new generation of ASIC," which spawned a very lucrative industry - integrated circuit design.
3.Advances in integrated circuit devices led to the development of high-end technical areas adjacent to greatly reduce the flat-panel displays, the cost of MEMS sensors, radios and other devices and passive components. Under these conditions, system integrators again control system design and product integration.
4.The rise of Internet applications and mobile intelligent terminal, led to the development of widespread deployment of fiber optic cable and a variety of wireless technologies, to achieve unprecedented global mobile Internet. This ecosystem has created "things" in this emerging market, and innovative product manufacturers, telecom companies, data and information distributors and content providers are competing for dominance of the market.
Semiconductors are the cornerstone of all of these applications, all without the support of innovation in the semiconductor industry.
二、Global Technology Roadmap for Semiconductors
The late 1960s, self-aligned silicon gate technology invention laid the foundation of the semiconductor specifications. Moore 1965 proposed biennial transistor replacement, "Moore's Law", and Dennard 1975's "Dennard's Law", to promote the growth of the semiconductor industry, until the early 2000s, which is the traditional geometries scaled (Classical Geometrically Driven Scaling) era. Scaled into equivalent basis (Equivalent Scaling) era is strained silicon, high-k metal gate, multi-gate transistors, compound semiconductor and other technologies to achieve these technologies to support the development of the semiconductor industry over the past decade and will continue support the future development of the industry.
（一）Device
Information processing technology are driving the semiconductor industry into the broader field of application, device cost and performance will continue to work with complementary metal oxide semiconductor (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) dimensions and extensions are closely related.
Strained silicon, high-k metal gate, multi-gate transistor is now widely used in the manufacture of integrated circuits, to further enhance device performance will focus on the elements of III-V materials and germanium. Compared with silicon devices, these materials will enable devices with higher mobility. In order to utilize the advantages of perfect silicon platform, expected that the new high-mobility materials will epitaxy on silicon substrates.
2D Scaling eventually during the 2013 International Technology Roadmap for Semiconductors (ITRS) reaches its fundamental limits, either logic or memory devices are exploring how to use the vertical dimension (3D). 3D structure and binding apparatus of the low power device will turn "3D scale energy (Power Scaling)" times, the number of transistors per unit area is increased by the multilayer stack will eventually transistor.
Unfortunately, no new interconnection breakthrough because there is no viable material has a lower resistivity than copper. However, progress in addressing carbon nanotubes, graphene and other endless wrapping material composition (edgeless wrapped materials) aspects of development "ballistic conductor" (ballistic conductor) to provide basic protection for, which may appear in the next decade.
The three-dimensional multi-chip package provides for reducing the interconnect resistance possible way, mainly by increasing the conductor cross-section (vertical) and reducing the length of each interconnect path.
However, CMOS or equivalent transverse dimension currently under study (equivalent device) will eventually reach the limit of extension. New opportunities for the future of semiconductor products that: First, through heterogeneous integration of new technologies to expand functionality CMOS platform; second is to develop a new generation of information processing paradigm supported devices.
（二）System Integration
Systems integration to data from the operation, PC-centric model into a highly diversified mobile communications mode. IC design being driven from a performance target to target with low drive change, making a variety of technologies in a limited space (such as GPS, phones, tablet computers, mobile phones, etc.) can be heterogeneous integration, which revolutionized the semiconductor industry . Briefly, in the past, the performance goals are unique; Today, the goal of minimizing the power consumption of integrated circuit design lead.
System-on-chip and system level packaging products have become the main driving force for the semiconductor industry. Over the past few years, production of smart phones and tablet computers has exceeded the yield of the microprocessor. The foundation relies on heterogeneous integration "extend Moore" (More Moore, MM) equipment and "More than Moore" (More than Moore, MtM) integrated elements.
For example, at present, micro-electromechanical systems (MEMS) devices are integrated into cars, video projectors, tablet PCs, smart phones and game platforms and other types of systems. Under normal circumstances, MEMS devices for the system adds useful features to enhance the core functionality of the system. For example, MEMS accelerometers smartphone meter can detect the phone vertically and rotate the image displayed on the screen. Additional features introduced by MEMS improved user interfaces, but the phone can still run without it. In contrast, if there is no MEMS devices based on digital light projection technology (digital light projector, DLP) recorders and inkjet printers will not work. Multi-mode sensing technology has become an integral part of mobile devices, a key driving force things. .
Rapid progress numeric data (digital data) and connection technology for medical services to bring about change. Silicon, micro-electromechanical systems and optical sensor technology are making this revolution possible.
Mobile phones can already provide a lot of health information. Accelerometers can track movement and sleep, when the user touches the phone, built-in optical sensors that can sense the heart rate. In the phone's camera can be used for different purposes, such as checking the calorie content of food, or facial expression recognition based on their emotions. A wide range of mobile applications have been developed to analyze these data, and use easy to understand and operate the way back to the consumer.
Looking at the next 7-15 years (after 2020) the development of equipment and systems, based on a new principle of the device will support the new architecture. For example, the spin wave devices (spin wave device, SWD) is a magnetic logic device, rotate the use of collective oscillations (spin waves) information transmission and processing. Spin wave device input voltage signal is converted into spin waves, spin-wave calculation, the spin-wave output is converted into a voltage signal. In a single core configuration, the massively parallel data processing frequency by open multiple different information for each frequency channel at very low power to perform. In addition, some new equipment to promote the creation of new architecture. For example, storage-class memory (storage-class memory, SCM) is a combination of solid state memory (performance and robustness), archiving capabilities and low-cost advantages of conventional hard disk magnetic storage devices. Such a device requires a nonvolatile memory (nonvolatile memory, NVM) technology, with a very low manufacturing cost per bit of storage space.
（三）Manufacture
Driven by the expansion of the dimensions, integrated circuit manufacturing precision will reach the level of a few nanometers in the next 15 years. Use any technique to measure the physical properties of the wafer has become increasingly difficult, by correlating the process parameters and device parameters will be essential to achieve this task. By controlling equipment and process reproducibility and stability, precise control of feature size and other process parameters have been able to complete.
Fab is continuously driven by the data, the amount of data, communication speed, data quality, availability and other requirements are understood and quantified. 300 mm wafers to 450 mm from the transformation challenges. Should focus on for 300 mm and 450 mm common technology development, fab 450 mm technology will apply to 300 mm wafers due to improvements in technology and benefit.
System-on-chip and system-level integration package will continue to heat up. Increased integration of promoting re-integration test solutions to keep the cost of testing and product quality specifications. Optimization of test solutions may need to access and test the embedded module and the kernel. Providing high-quality grain for multi-chip package known good chip (KGD) technology has become very important, and become an important part of the test the technical and cost trade-offs.
三、Major challenge
（一）短The Challenge (now to 2020): performance
1、Logic
Complementary metal-oxide planar semiconductor (CMOS) traditional growth path will face serious challenges in terms of performance and power consumption.
Despite the high dielectric metal gate (high-k/metalgate, HKMG) the introduction of equivalent gate oxide thickness (equivalent gate oxide thickness, EOT) reduction remain challenging in the short term. Integration of high dielectric material, while limiting due to the band gap narrowing caused by wearing the gate tunneling current increases, will also face challenges. Complete gate stack material systems need to be optimized in order to obtain the best device characteristics (power and performance) and reduce costs.
New device structures, such as multi-gate metal oxide semiconductor field effect transistors (MOSFETs) and ultra fully depleted silicon on insulator (FD-SOI) will appear, a very challenging problem is that these ultra-thin metal oxides The thickness of the semiconductor field-effect transistors (MOSFETs) control. Solve these problems should improve circuit design and system architecture in parallel.
Some high mobility materials such as Ge and III-V group elements have been considered to be upgraded or replaced with CMOS logic applications in silicon channel. With low body traps and low power leakage, non-staple 扎费米 level (unpinned Fermi level), low ohmic contact resistance high dielectric metal gate dielectric is a major challenge.
2、Memory devices
Challenge dynamic random access memory (DRAM) that, in the feature size reduction, the application of high-k dielectric, low-leakage design of the access devices, and the condition of low resistivity material for the bit lines and word lines, with a suitable storage capacitance. In order to increase the bit density, and reduce production costs, the drive unit 4F type requires a high aspect ratio and a non-planar transistor structure.
Flash has become a key scaling, the front-end process materials and processing (photolithography, corrosion, etc.) and technology (Front End Of Line, FEOL) new driving force of technology. Short-term, sustainable development depends on the density flash tunnel oxide (Tunnel Oxide) as well as the thickness of thin dielectric integration.
In order to ensure the maintenance and durability requirements of the charge, the introduction of high dielectric materials will be necessary.超过 256 GB of 3-D NAND flash memory to maintain cost-effective while ensuring multi-level cell (Multi Level Cell, MLC) and a certain reliability remains a formidable challenge. New challenges also include the evolution of a new concept and a new type of memory storage of manufacturing such a magnetic random access memory (MRAM), phase change memory (PCM), resistive random access memory (ReRAM) and ferroelectric random access type access memory (FeRAM).
3、High-performance, low-cost RF and analog / mixed-signal solutions
Promote the wireless transceiver integrated circuit CMOS technology and millimeter wave applications (high-k dielectrics and strain engineering) may need to keep the device mismatch and the 1 / f noise in an acceptable range of technologies. Other challenges include the integration of cheaper and high-density integration of passive components, integrated and efficient silicon chip passive network technology MEMS, development of devices based on low-cost non-silicon (GaN).
With increasing complexity and chip operating frequency the signal isolation reduces the supply voltage, the digital and analog chip area becomes more and more important. Noise may need more innovation, for example through technical design, solve every thousand ohm cm high resistivity base level power supply and ground connection problems.
Many variations of the material and structure of the guide, such as a digital road map, and a multi-gate thin-film silicon on insulator (silicon on insulator, SOI) attenuation behavior change or switch the RF and analog components. There are complex trade-offs in optimizing RF, high-frequency and AMS performance, as well as a steady decline in the supply voltage, etc., a huge challenge for the IC design.
4、32 and 22 nm half-pitch and below
Lithography is becoming very expensive and the most challenging technology. Half pitch of 22 nm lithography, the use of photolithography spacers 193 nm or more modes of immersion lithography machine, to be applied to overcome the limitations of a single mode, but a very large mask error enhancement factor (mask error enhancement factor, MEEF), wafer line edge roughness (line edge roughness, LER), design rule constraints and higher costs. A wavelength of 13.5 nanometers deep ultraviolet lithography (Extreme-UV lithography, EUVL) is the industry's official push Moore expectations.
Carved deep ultraviolet challenges are: lack of high-power source, high-speed photoresist mask defect and flatness bring high latency. Further challenges include increasing the numerical aperture DUV systems to more than 0.35, and the possibility of imaging systems improved by increasing the number of mirrors.
Multiple electron beam maskless lithography technique (Multiple-e-beam maskless lithography) mask has bypassed the problem, remove the restriction of design rules, and provides the potential for manufacturing flexibility. High-resolution images on the display and CD control progress has been made. Manufacturing tools to master the timing, cost, defects, accurate overprint, the photoresist is subject to further development of other areas.
Direct self-assembly (Direct Self-Assembly, DSA) technology for new progress, but defects and urgent need to improve the positioning accuracy.
Other challenges include: lithography method (lithography and etching) in the light-emitting resistor (LER) gate length CD control and suppression, of the new gate materials, non-planar transistor structure, the photoresist and deep UV light-emitting resistor lithography
5、The introduction of new materials
Because of the low dielectric material (including a porous material and the air gap) must have sufficient mechanical strength to withstand cutting, packaging and assembly, taking into account the etch and chemical-mechanical polishing (chemico-mechanical polishing, CMP) process, the dielectric material of low dielectric becomes more important to reduce electrical damage. Metals, thin, conformal low resistivity barrier metal needs to be integrated with copper, in order to achieve low resistivity and high reliability.
6、Power Management
Most application stage, power management is the most important issue nowadays. Because the number of transistors in each generation will increase exponentially, but the chip package, a cost effective heat dissipation remains almost unchanged. In order to maintain an active and reduces leakage power system to achieve the appropriate circuit technology will be extended to the requirements of the system design, computer-aided design tools (computer aided design, CAD) improvements, leakage power reduction and performance requirements of the new device architecture level .
（二） Short-term challenges (now to 2020): Cost-effectiveness
1、Lithography
Although the wavelength of 13.5 nm deep ultraviolet lithography is an industry official goal, but deep ultraviolet lithography source of power must be achieved in order to have a high cost-competitive in the 10 nm and above the level of technology. If the multiple electron beam maskless lithography exposure technique can be maintained for each pass, the process cost, and mask-based exposure tool with a similar trace, it may be the most economical choice. After the introduction of the process the number of masks less, 193 nm immersion lithography digital storage architecture (DSA) became popular.
2、Front-end process
We need to achieve low parasitics, continue to narrow gate pitch, the next generation substrate size adjustment (adjusted to 450 mm wafers), and using breakthrough technology to meet the challenges of lithography.
3、Factory Integration
The main challenges include: First, to deal with rapidly changing, complex business needs; Second is to manage the increasing complexity of the plant; Third declining marginal benefits while achieving economic growth targets; fourth, plant and equipment to meet the reliability, functionality , efficiency and cost requirements; five is the use of cross-border cross-factory integration technologies, such as 300 mm and 450 mm with in order to achieve economies of scale; six is to solve the unique challenges of migration to 450 mm wafers.
4、Meet changing market requirements of cost
Assembly and packaging challenges include three-dimensional integrated chip stack (test: access, cost, and known-good chip, three-dimensional packaging and packaging, testing, access to a single wafer or chip).
5、Environment, safety, health
Environmental safety and health challenges facing the field are: Management and Efficiency of chemicals and raw materials; process and equipment management; facilities technical requirements; product management; life product recycling / recycling / reproduction.
6、Measure
Plant level and corporate level measurement integration: measurements should be carefully chosen, statistical sampling must be optimized to meet the cost-based owner of the process control (cost of ownership, CoO).
（三）Long-term challenges (2021-2028): The performance boost
Highly miniature metal oxide semiconductor field effect transistors (MOSFETs) to provide sufficient drive current, with enhanced thermal velocity and injected at the source seems quasi-ballistic operation is necessary. Therefore, high-speed transmission channel materials, such as III-V compounds or silicon germanium on the substrate in narrow channels, or semiconductor nanowires, carbon nanotubes, graphene, or other material will be developed. Atypical complementary metal oxide semiconductor (CMOS) devices need to be integrated on a single CMOS platform physical or functional ground. Such integration requires exotic semiconductor epitaxially grown on the silicon substrate, which is challenging. Ideal material or device performance must be maintained at the high temperature and corrosive chemical processing. In the early technology development, reliability issues should be established and solved.
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